1. Technical Field
The present invention relates to an electro-optical device including thin-film transistors and storage capacitors arranged above an element substrate and an electronic apparatus including the electro-optical device.
2. Related Art
Among various electro-optical devices is an active matrix-type liquid crystal device. In the liquid crystal device, a liquid crystal is held between an element substrate 10 shown in FIGS. 16A and 16B and a counter substrate (not shown). The element substrate 10 includes a plurality of pixel regions 1e corresponding to intersections of gate lines 3a (scanning lines) and source lines 6a (date lines). The pixel regions 1e include thin-film transistors 1c for switching pixels and pixel electrodes 2a electrically connected to drain regions 6b of the thin-film transistors 1c. The alignment of the liquid crystal is controlled for each pixel in such a manner that image signals are applied to the pixel electrodes 2a from the source lines 6a with the thin-film transistors 1c. The pixel regions 1e further include storage capacitors 1h including lower electrodes 3c and upper electrodes 6c, the lower electrodes 3c being portions of capacitor lines 3b, the upper electrodes 6c being extending portions of the drain regions 6b. The storage capacitors 1h further include dielectric layers 4c that are usually portions of a gate insulating layer 4 shared by the thin-film transistors 1c. An increase in the capacitance per unit area of the storage capacitors 1h enhances charge-holding properties thereof, reduces the occupancy area thereof, and increases the aperture ratio of the pixels.
In order to increase the capacitance per unit area of storage capacitors without reducing the dielectric strength of gate insulating layers shared by thin-film transistors, it has been attempted that the thickness of the gate insulating layers is increased and the thickness of dielectric layers is reduced.
For example, JP-A-9-160070 (hereinafter referred to as Patent Document 1) discloses that anodic oxide films on lower electrodes are used as dielectric layers of storage capacitors and a gate insulating layer has a multilayer structure including anodic oxide films on gate electrodes and a silicon nitride layer overlying upper electrodes.
JP-A-2005-217342 (hereinafter referred to as Patent Document 2) discloses that the following portions are used as dielectric layers of storage capacitors: thin portions that are formed in a gate insulating layer in such a manner that the gate insulating layer is partly removed by etching using a half-tone mask.
JP-A-2004-45811 (hereinafter referred to as Patent Document 3) discloses that a dielectric layer for forming storage capacitors is formed, regions for forming thin-film transistors are removed from the dielectric layer, and a gate insulating layer is then formed.
Japanese Patent No. 3106566 (hereinafter referred to as Patent Document 4) discloses a technique for forming top-gate thin-film transistors in which semiconductor layers, portions of a gate insulating layer, and gate electrodes are arranged in that order from the bottom. In this technique, a first insulating layer made of silicon dioxide is formed by the thermal oxidation of a semiconductor layer, the gate insulating layer is formed in such a manner that a second insulating layer made of silicon nitride is deposited on the first insulating layer by a chemical vapor deposition (CVD) process, and the second insulating layer is partly removed by etching in such a manner that portions of the gate insulating layer that overlap with channel regions are covered with a resist mask, whereby thin portions are formed in the gate insulating layer. The thin portions are used as dielectric layers of storage capacitors.
Patent Documents 1 to 4 describe the reduction of the thickness of the dielectric layers but contain no information about the reduction of the dielectric strength of portions of the dielectric layers having a reduced thickness, the portions being sandwiched between the upper electrodes and end portions of the lower electrodes. The end portions of the lower electrodes have a stepped shape and therefore the dielectric layers have stepped portions corresponding to the stepped shape. Therefore, when voltages are applied between the lower and upper electrodes, electric fields cannot be uniformly generated across the dielectric layers and therefore are concentrated on the end portions of the lower electrodes. This causes a reduction in dielectric strength or dielectric breakdown (short circuits). The growth direction and the deposition rate of the dielectric layers depend on the morphology of components disposed under the dielectric layers. Therefore, the dielectric layers have nonuniform regions which extend over the end portions of the lower electrodes and which have different properties. The nonuniform regions can cause a reduction in dielectric strength.